1. Field of the Invention
The field of the invention is data processing, or, more specifically, methods, apparatus, and products implemented in or as computer peripheral expansion apparatus.
2. Description of Related Art
The development of the EDVAC computer system of 1948 is often cited as the beginning of the computer era. Since that time, computer systems have evolved into extremely complicated devices. Today's computers are much more sophisticated than early systems such as the EDVAC. Computer systems typically include a combination of hardware and software components, application programs, operating systems, processors, buses, memory, input/output devices, and so on. As advances in semiconductor processing and computer architecture push the performance of the computer higher and higher, more sophisticated computer software has evolved to take advantage of the higher performance of the hardware, resulting in computer systems today that are much more powerful than just a few years ago.
One of the areas of computer technology that has seen advancement is peripheral interconnect apparatus. Blade interconnections in particular have been developed to compact a very large quantity of computing power into a small physical space. As an aid to explanation, FIG. 1 sets forth a schematic functional block diagram of example prior art peripheral expansion apparatus implemented in the blade form factor, including a host blade (302) and three blade peripheral expansion units (‘BPEUs’) (304, 306, 308). The BPEUs are connected to the host blade through three separate peripheral interconnect buses (‘PIBs’) (326, 328, 330). PIB (326) separately connects the host blade to peripheral interconnect devices (‘PIDs’) on BPEU (304); PIB (328) separately connects the host blade to PIDs on BPEU (306); and PIB (330) separately connects the host blade to PIDs on BPEU (308). Each PIB requires a full set of PIB conductors and a full set of PIB pins on connectors (331, 332, 333) among the host blade and the BPEUs. Moreover, each PIB (326, 328, 330) is configured to carry data communication between the host blade and only one type of BPEU, and the PIBs will not support more than one PID at a same PIB address without contention.